1. Field of the Invention
This invention relates to testing systems, and more particularly, to testing PCI devices.
2. Background of the Invention
An Application Specific Integrated Circuit (ASIC) is used in various applications to perform certain logical functions. Before an ASIC is commercially made available, it is typically tested in a laboratory/manufacturing environment. A testing system (may also be referred to as “tester”) is typically used to test ASIC functionality and logic therein. ASIC testing includes static measurements like voltage and current and dynamic measurements like timing and jitter.
Typical timing measurements include data set-up time and data hold time. Timing measurements use a reference signal, typically a clock, and a transition signal, typically data. A clock is a signal that has a repeating pattern of logic 1 (high voltage) for a period of half clock cycle and logic 0 (low voltage) for a period of half clock cycle. When a signal makes a transition from logic 0 to logic 1 then a positive edge is made. Similarly, when the signal makes a transition from logic 1 to logic 0 then a negative edge is made.
Data set-up time is defined as the amount of time a data signal is stable after a clock edge. Similarly, data hold time is defined as the amount of time a data signal is stable before a clock edge. The clock edge can be positive edge or negative edge.
In a PCI-X device, data set up and data hold values are measured with respect to a positive clock edge. A PCI-X device is one that complies with the PCI-X standard, and the standard is incorporated herein by reference in its entirety. An example of such a device is a host bus adapter that interfaces with a host computing system via a PCI-X bus.
In a conventional PCI-X device, output data transitions only once during a PCI-X clock cycle. A tester measures output data set-up timing and data hold timing on the fly with respect to the positive edge of the PCI-X clock.
PCI-X, version 2.0 is now commonly used as a bus standard for various devices, including HBAs. In a PCI-X 2.0 device, data transitions twice in a single clock cycle. Reference signals for a PCI-X 2.0 device are denoted as first strobe and second strobe signals. Output data set-up timing values and data hold timing values are defined with respect to the first strobe and second strobe signals. This method of transmitting output data with respect to other output signals, first strobe and second strobe, is called source synchronous mode (SSM). Conventional single tester cycle and a single tester pass are not adequate to measure the data set-up and data hold timing values in a PCI-X 2.0 device.
Therefore, what is needed is a method and system for measuring source synchronous mode (SSM) data set-up and data hold timing values.